Fiction | Playful Jaguar inside Xbox One and PS4: Architecture




Fiction | Playful Jaguar inside Xbox One and PS4: Architecture

On the processor AMD based Jaguar two latest games consoles. Microsoft Xbox One, a guest of the creators who recently visited our readers. And, of course, Sony PlayStation 4 (PS4). What exactly makes this processor so attractive to the gaming industry? Perhaps the answer to this question can be found in its technical features. We continue to look at the game from the “iron”. And today, a closer look at the architecture of the processor involved in the new generation of video game consoles.

Two architecture efficient one

Архитектура Bulldozer

Nowadays, the development of microprocessor architecture rests on the restriction imposed by power consumption. The processor should be clearly positioned for use in specific devices. The reason for this indicator TDP. TDP figure describes the ability of the cooling system to remove heat. It should be above the maximum heat dissipation chip, but too much stock reduces the effectiveness of architecture.

For example, the architecture of Intel Core (Sandy / Ivy Bridge) can operate efficiently while consuming energy in the range from 13 to 130 watts. It turns out that it can be applied to devices consuming more or less power. But more efficiently develop an architecture whose heat (and thus power consumption) is more consistent indicator TDP. In other words, it is preferable that the CPU performance match each other. This is advantageous both technically and from the economic side.

And AMD, Intel, and follow this “rule of order of magnitude.” Therefore, each of the world’s leading chip maker has two different microprocessor architectures. Intel offers the Atom for low-power and high-performance Core computers. In 2010, AMD introduced the Bobcat, cost related to energy resources, and Bulldozer for systems with high performance.

And Bobcat, Bulldozer and are updated annually. In 2011, there was Bobcat, has found application in a single crystal systems (SoC) Ontario and Zacate in the platform Brazos. Last year, AMD announced the Brazos 2.0. It uses a slightly updated, but very close to pozaproshlogodnih SoC based on the Bobcat. A recently presented APU Kabini and Temash , based on the first major update Bobcat: core Jaguar.
Jaguar and Bobcat: similarities and differences

Архитектура Jaguar

At the core processor Jaguar similar to its predecessor Bobcat. This architecture still requires the simultaneous launch of two teams or instructions for execution (dual-issue). In this case, it is characterized by the extraordinary performance of teams (out-of-order): this means that the instructions are executed out of order, and it is ready to run. In short, the basic architecture is based on the idea that AMD introduced in 2010.

All the same, the first level cache (L1); input and output execution units are present, as before. Note that the architecture of ARM Cortex A9 allows you to simultaneously run for the execution of three instructions (three-issue). In the Cortex A15 is applied and order execution. Leading resource AnandTech known technical analyst Anand Lal Shimp (Anand Lal Shimpi) believed that AMD will offer the world something like that.

AMD has miniaturized the production process of its chips to 28-nanometer. This is very interesting, but the main emphasis corporation has made to improve the performance of Jaguar in comparison to its predecessor, while maintaining the same TDP. What prompted AMD to do lower heat its chips?

The fact that the Bobcat architecture focused on low-cost and small-sized computers, particularly netbooks and nettops. Jaguar’u also have to – in full accordance with the spirit of the times – to find their place in a more compact devices: tablets. AMD is not going to create a SoC for smartphones, but the market for tablets based on Windows 8 (and perhaps, Android?) Is very attractive for the company. As to such devices shall not be required compatibility with cellular networks (not least because of their comparatively lower price), AMD can easily offer an alternative architecture of Intel Atom.

With most types of workload modern processors still perform less than one instruction per cycle (cycle). Rather, it is for this reason that AMD did not see the point in introducing the architecture of the simultaneous launch of three instructions (three-issue). After all, it would require to increase the power consumption, and this approach is not feasible for processor-based mobile devices.

In addition, Jaguar’y could become so powerful that they would no longer feel the difference between them and the family of Bulldozer. And as noted in the beginning of the story, “average” architecture unprofitable either from an engineering or an economic point of view. Looks much more attractive model, in which the chip maker has a separate architecture for powerful computers and separately for compact devices. In the first case focuses on the performance in the second – power consumption and heat dissipation, things are closely interrelated.

The transition to three simultaneous loading instructions, of course, increase productivity, but will not allow AMD processors to take their place in the plates. Therefore, says Anand Lal Shimp, increasing the power of deferred to the future. On the background of the “trehinstruktsionnyh» ARM, and Jaguar, and Intel Silvermont look a little old-fashioned. But the comparison should take into account the fact that AMD and Intel are trying hard to reduce the power consumption of its processors. As for ARM, within the limits of this architecture, the focus is on increasing productivity.

Jaguar buffer has four cycles x 32 bytes. If you find a cycle, instead of extracting repeatedly used in a series of instructions from the cache of the first level, they are extracted from this small buffer. Should not be regarded as a piste cache (trace cache) or micro cache (micro-op cache). Things are far more prosaic. The advantage of this buffer is only that the instruction cache is not loaded every time you access the instructions that came with the cycle. This means lower power consumption of the processor, rather than enhance its performance as it may seem at first glance.

Before you enter the market, the work of the processor repeatedly modeled. During simulation there are weaknesses in the processor. Even when the processor is designed, some of them still remain. And they were eliminated in the next generations of chips.

You can, of course, for years, even decades to bring the processor to the ideal state. But the manufacturer has to think not only about how to offer the market the best possible processors. He always takes account of limitations, among which the main role played by the cost and schedule in which to meet. If the manufacturer possessed an unlimited budget, it could eliminate all the bottlenecks in their development. But that would require an eternity. In reality, the trade-offs.

One example of such a compromise may be the fact that AMD has stopped on the simultaneous launch of two (instead of three) instructions. The company also refused to cache buffer in favor of micro-cycles, which is a simpler solution. Rather, the company’s engineers felt that too much energy is wasted on cycle times, and the addition of a special buffer for these problems is the best solution in terms of energy efficiency, cost and complexity of implementation.

AMD has also improved device anticipatory (proactive) fetch instruction cache (teams). This appeal to the design of Bobcat and effort to find its characteristics used in the framework of the new architecture of Jaguar. This time, AMD did not have to create a fundamentally different architecture. She was enough just to create a Bobcat-based architecture, which will deal with the same challenges better than its predecessor. Instruction buffer between the instruction cache and decoders Jaguar became more. But it’s a half-hearted decision. In Bulldozer fetch and decode stages are generally divided.

In Jaguar implemented 40-bit physical addressing and support for new instructions: SSE4.1/4.2, AES, CLMUL, MOVBE, AVX, F16C, BMI1. Bobcat weak spot was that its decoder to limit the maximum frequency. In Jaguar, added an additional step of decoding, allowing AMD to implement prescribed frequency in the 28-nanometer technology.

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