Imec demonstrates transistor techniques 7nm




The Belgian research institute IMEC has shown during a meeting on chip development in Kyoto transistors that can be produced on 7nm. The transistors are an evolution of the FinFET technology that debuted at 22nm.

At the VLSI Symposium 2015 in the Japanese city of Kyoto IMEC showed two transistor types that can be used for 7 nm node. Researchers showed transistors with channels of silicon germanium, wherein the gates are formed is referred to by a process that RMG-HK. They also produced with transistors that are not finfets, but with channels of nanowires with the gate wrapped around it works. It is a layer of silicon sacrificed to make way for a gate which surrounds the channels. That should, as with FinFET gates, a larger area of ​​worry gates in order to realize smaller, faster and more economical transistors.

The GAA-technique was demonstrated both in a CMOS process as in an SOI process. Additionally showed the Imec researchers finfets whose gate fins were formed by a combination of self-alignment and double patterning. These were equipped with quantum wells of strained germanium. That would lead to better performance: in the lab would be 40 percent more power transistors which can switch earlier than strained germanium transistors.

gate all around nanowire

The newest transistors currently produced on 14nm, while around 2016 should follow the 10nm node. Transistors that are made according to a process would have to 7nm-on there again follow. Current techniques, however, can not simply be reduced, for reasons including the IMEC to search for alternatives. The Belgian research institute does not only that several chip manufacturers and designers collaborate with the institute based in Leuven. International research has also Taiwanese, Chinese and Dutch branches: the latter is part of Holst Centre.


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