Intel adds a third step to release cycle for new processors

Mar

24

2016

Intel seems to be tick-tock naming goodbye to have said. The chip company now uses the term “process-optimization-architecture ‘for the cycles of successive processor generations. Intel adjusts the cycle of three stages, in any case allow at 14 and 10nm.

Intel are tick-tock cadence-unleashed, was already known . In its annual Form 10-K document on the financial situation, which Motley Fool report , the company said, however, now officially adopt a three step cycle. This means that there is a new architecture, followed by a generation in which the architecture is optimized after the switch to a new process.

The tick-tock cadence implied that Intel one year switched to a new chip architecture and the following year reduced the production. Every two years, Intel therefore switched to a smaller-nm generation, but now it has become rather 2.5 to 3 years. However, Intel will continue to annually release a new processor generation.

“We expect the time in which we use to extend our 14nm- and upcoming 10nm process technology to optimize our products and processes and at the same time to continue to meet our annual cadence for market introductions,” Intel wrote.

The communication is in line with rumors that Intel introduced three processor generations 10nm Cannon Lake, Icelake and Tiger Lake. The 14nm processors span three generations; After Broadwell and current Skylake later this year Kaby Lake. The release of tick-tock demonstrates the difficulty to maintain the Moore’s Law. The limits of current immersion lithography into economically viable is coming into sight with next practices, but the machines for the following technology, extreme ultraviolet, is still tinkering.

Intel is working with the Dutch ASML to those machines and expect them to be able to put in the 7 nm production. It is not known whether a tick-tock cadence again within reach. after 7 nm are also new difficulties for further reduction into play. Intel will thereby expected to become increasingly need to have more of optimizations to the architecture processor for improvement, rather than reduction of the nodes.

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