TSMC starts 5nm test production in April with up to fourteen layers of euv




TSMC has prepared its facilities in April of next year for risk production at 5nm and the company then uses euv technology for up to fourteen layers. The switch would allow for 17.7 percent faster chips.

It is about risk production , with which it can take another year for the mass production of chips to start. TSMC itself expected earlier that this would be the end of 2019, beginning of 2020. Based on tests with Arm A72 cores, TSMC concludes that the 5nm node can produce 14.7 to 17.7 percent higher speeds compared to the 7nm node and that the chip surface can decrease by a factor of 1.8.

The Taiwanese chip company has, according to EETimes , the first tape out of a 7nm + chip for a customer behind it. The 7nm + process is TSMC’s successor for the current 7nm production process, which produces, among other things, chips for Apple’s A12 Bionic and Huawei’s Kirin 980. Compared to 7nm, 7nm + results in a decrease in consumption of 6 to 12 percent, but it is not known what the speed improvements can be.

TSMC has euv for both 7nm + and 5nm, but at 7nm + this is only for four layers and for 5nm already for fourteen layers of chip production. The costs go up at the same time, according to a source of the EETimes. The total cost for a 7nm design would currently be $ 150 million, but this would increase to 200 to 250 million at 5nm. Ultimately, these costs have to decrease because ejects require less masks, which cost a lot of money.

TSMC seems to be the most advanced of the chip companies with its euv integration, although Samsung also uses euv for its 7nm node. Intel, however, takes a wait and see attitude and GlobalFoundries has completely stopped developing both 7nm and euv. The euv machines from the Veldhoven company ASML use extreme ultraviolet light to apply small patterns with a single exposure. This works time-saving and should yield better results than multipatterning in the current process based on immersion lithography. Euv can initially be used for several chip layers, but as the technique is improved, it must be possible to use it for more layers.



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